The subject matter herein relates to synchronization of electrical signals, and more particularly, to synchronization of digital signals using a digital phase-locked loop.
It is often necessary to synchronize one electrical signal with another relative to the phase of the two signals. In a digital system having multiple digital subsystems connected or operating together, for example, multiple clocks may be used to operate different parts of the digital circuitry that must function cooperatively. For better cooperative functioning, the clocks are commonly synchronized using a digital phase-locked loop (DPLL), so that the components of the circuits operated by the clocks are xe2x80x9cclockedxe2x80x9d at the same time, or within a desired skew of each other.
Different phase-locked loop (PLL) schemes are used for different purposes in different situations. When a heretofore unencountered situation occurs, a new PLL or DPLL needs to be developed.
It is with respect to these and other background considerations that the subject matter herein has evolved.
The subject matter herein discloses circuitry for synchronizing clock signals, such as a low-cost digital phase-locked loop (DPLL) for synchronizing clock signals in digital circuitry. The description of the DPLL in a hardware descriptive programming language (e.g. Verilog or VHDL) may be scalable and parameterizable, so that it may be quickly adapted for different applications.
The DPLL generally samples a xe2x80x9creference clockxe2x80x9d immediately before, approximately at and immediately after an anticipated transition point of a xe2x80x9cgenerated clockxe2x80x9d to determine whether the reference clock transitions early, approximately on time (i.e. within an acceptable tolerance or range) or late relative to the transition point of the generated clock. In response to the sampling, the DPLL generally generates an xe2x80x9cearlyxe2x80x9d signal or a xe2x80x9clatexe2x80x9d signal or neither signal. The early and late signals indicate whether the period of the generated clock needs to be shortened or lengthened, respectively, generally by the amount of one period of an xe2x80x9cinput clock,xe2x80x9d from which the generated clock is generally generated. When the DPLL generates neither the early nor late signal, then the reference clock evidently transitioned within the acceptable tolerance of the transition point of the generated clock, so no adjustment needs to be made to the generated clock.
The reference clock is generally sampled during each period of the generated clock, which is generally almost the same as the period of the reference clock. In this manner, generally in every period of the reference clock, the DPLL determines whether to lengthen or shorten one period of the generated clock by one period of the input clock, or leave the generated clock unchanged. The generated clock may be generated from an intermediate xe2x80x9coutputxe2x80x9d clock, which is generated from the input clock, so the one period of the generated clock may be adjusted (lengthened or shortened) by actually making the adjustment to the output clock.
The DPLL generally uses phase detector circuitry with a plurality of xe2x80x9cregistersxe2x80x9d to effectively xe2x80x9cregister,xe2x80x9d or xe2x80x9clatch,xe2x80x9d the reference clock immediately before, approximately at and immediately after the approximate point at which a transition edge occurs in the generated signal. The point at which the edge occurs in the generated signal is the point at which an edge xe2x80x9cshouldxe2x80x9d occur in the reference signal, when already synchronized. For example, one of the registers generally registers the state of the reference clock at a point shortly before the point at which the reference clock would transition if already synchronized. Another register generally registers the state of the reference clock at a point almost at the anticipated transition point. A third register generally registers the state of the reference clock at a point shortly after the transition point. If the transition point is at a positive edge (a low-to-high transition) of the reference clock, and all the registered states are xe2x80x9clow,xe2x80x9d then it is evident that the low-to-high transition of the reference signal occurred late with respect to the transition of the generated clock, so the xe2x80x9clatexe2x80x9d signal is asserted. On the other hand, if all the registered states are xe2x80x9chigh,xe2x80x9d then it is evident that the low-to-high transition of the reference clock occurred early, so the xe2x80x9cearlyxe2x80x9d signal is asserted. If, however, one or two of the registered states are low and the rest high, then the transition occurred within the acceptable tolerance, so neither the early nor the late signal is asserted.
The DPLL may synchronize the phases of multiple signals, each having a different period. For example, in one embodiment, the input clock has a period significantly shorter than that of the output clock and the reference clock, and the output clock has a period significantly shorter than that of the reference clock. Additionally, the period of the reference clock may be an integer multiple of the period of the output clock, which is an integer multiple of the period of the input clock. Therefore, since the period of the output clock is significantly smaller than that of the reference clock, the sampling points of the reference clock are relatively close to the transition point of the reference clock (and therefore to the transition point of the generated clock when synchronized) compared to the overall period of the reference clock. Additionally, since one of the periods of the output clock (and of the generated clock) is shortened or lengthened, when needed, by one period of the input clock, the change to the period of the output clock is generally relatively small compared to the overall period of the output clock and even smaller compared to the period of the reference clock. The change to the period of the output clock (i.e. one period of the input clock) is generally an amount less than the acceptable tolerance, so that the change to the period of the output clock can bring the transition point of the output clock (and of the generated clock) within the acceptable tolerance of the transition point of the reference clock without overshooting it.
Additionally, various parameters of the DPLL, as set forth in the code in the hardware descriptive programming language (e.g. Verilog or VHDL), can be changed to adapt the DPLL for a variety of applications, so that the DPLL operates with almost any given frequencies for the input, output, generated and reference clocks, though generally retaining the above-stated relationships between the clocks. In various applications, the parameters are set in a module file, written in the hardware descriptive programming language (such as Verilog or VHDL), that defines the digital circuit. For example, since the clocks are digital, the input clock can be xe2x80x9cdividedxe2x80x9d by any appropriate means, such as by a digital counter, to generate the output clock. Changing the count of the counter causes a related change to the output clock (i.e. xe2x80x9cscalingxe2x80x9d the output clock). The count of the counter is determined by a value (i.e. a parameter) set in the code for the module file written in the hardware descriptive programming language for the digital circuit. Likewise, other counters and other components generally have values, or parameters, set in the code for the digital circuit for determining the time between registered states of the reference clock, or the amount by which the output clock is lengthened or shortened, among other variable features. In this manner, the DPLL is parameterizable, and xe2x80x9cscalable,xe2x80x9d for a variety of applications.
A more complete appreciation of the present disclosure and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.